Chapter 3 COA – Common Digital Components: Detailed Notes, Solved Examples & Hard Exam Questions

Hello dear students! Welcome to our detailed online lesson on Chapter 3 of Computer Organization and Architecture. Today we are going to learn about Common Digital Components — the building blocks that make up every digital computer. I will explain each topic step by step, give you worked examples, and test you with exam-style questions as we go. Ready? Let us begin!

1. Integrated Circuit (IC)

An Integrated Circuit (IC) is a small piece of silicon semiconductor material. We call this small piece a chip. Inside this chip, electronic components for digital gates are formed and connected together to build the required circuit. The chip is then placed inside a ceramic or plastic container, and very thin gold wires connect the internal circuit to external pins. These external pins are what we see on the IC package.

The number of pins on an IC usually ranges from 14 to 100. As technology improves over the years, more and more gates can fit inside a single chip. This progress is classified into different levels of integration.

1.1 Levels of Integration

Think of this like packing more and more books into the same-sized box. Here are the four main levels:

LevelFull NameNumber of GatesExamples
SSISmall-Scale IntegrationLess than 10 gatesBasic logic gates (AND, OR, NOT)
MSIMedium-Scale Integration10 to 200 gatesDecoders, Adders, Registers
LSILarge-Scale Integration200 to a few thousand gatesProcessors, Small memory units
VLSIVery-Large-Scale IntegrationThousands of gatesLarge memory arrays, Microcomputer chips
Key Exam Note: When the question says “MSI device,” the answer is a component that has between 10 and 200 gates. Decoders, adders, and registers fall under MSI. Processors fall under LSI. Memory arrays and microcomputer chips fall under VLSI. This classification is very frequently asked!

1.2 Classification of Digital IC Families

ICs are also classified by the logic family they belong to. The logic family decides the technology used to build the gates inside the chip. There are four major families you must know for your exam:

1. TTL (Transistor-Transistor Logic): This is the oldest and most widely used family. It has been in operation for many years and is considered the standard logic family. If someone says “standard IC,” they usually mean TTL.

2. ECL (Emitter-Coupled Logic): This family is the fastest among all. If a system needs very high-speed operation, ECL is the best choice. However, it consumes more power.

3. MOS (Metal-Oxide Semiconductor): This family allows very high component density. That means you can pack many more gates into a small area. It is suitable for circuits that need a lot of components in a small space.

4. CMOS (Complementary Metal-Oxide Semiconductor): This is the best choice when you need low power consumption. Battery-powered devices like watches, calculators, and mobile phones use CMOS technology because it uses very little power.

Important Formulas and Points to Remember for Exam:
TTL = Standard, most common
ECL = High speed (fastest)
MOS = High component density
CMOS = Low power consumption
SSI < 10 gates | MSI = 10–200 | LSI = 200–few thousand | VLSI = thousands+

Practice Questions – IC Basics

Q1 (MCQ): A decoder is classified under which level of integration?

(a) SSI    (b) MSI    (c) LSI    (d) VLSI

Q2 (MCQ): Which logic family is preferred for battery-operated devices?

(a) TTL    (b) ECL    (c) MOS    (d) CMOS

Q3 (Fill in the Blank): The logic family known for the highest speed operation is ________.

Answer

Q1 Answer: (b) MSI — A decoder contains between 10 and 200 gates. According to our classification, that places it in the Medium-Scale Integration (MSI) category. Remember: decoders, adders, and registers are all MSI devices.

Q2 Answer: (d) CMOS — CMOS technology is known for very low power consumption. Devices that run on batteries (like watches and calculators) need to save power, so CMOS is the clear choice here.

Q3 Answer: ECL (Emitter-Coupled Logic) — ECL is the fastest logic family available. When exam questions mention “high-speed operation,” immediately think of ECL.

2. Decoder

Now let us move to one of the most important combinational circuits — the Decoder. A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2ⁿ unique output lines. In simple words, if you give it a binary number as input, it will activate exactly one output line that matches that number.

Think of a decoder like a classroom roll call. The teacher calls a number (input), and only one student (output) stands up. If the teacher calls “3,” only student number 3 stands. All other students remain seated.

2.1 How a Decoder Works

The most common decoder is the 3-to-8 line decoder. It has 3 input lines and 8 output lines. Since 3 bits can represent 8 different combinations (from 000 to 111), each combination activates one unique output.

For a 3-to-8 decoder with inputs A, B, C and outputs D0 through D7:

Input CInput BInput AD0D1D2D3D4D5D6D7
00010000000
00101000000
01000100000
01100010000
10000001000
10100000100
11000000010
11100000001

Look at the table carefully. When input is 000, only D0 is 1. When input is 101, only D5 is 1. Exactly one output is HIGH at any time. This is the fundamental property of a decoder.

2.2 NAND Gate Decoder

A decoder can also be built using NAND gates instead of AND gates. The structure is the same, but the outputs behave differently. In a NAND gate decoder, the outputs are active LOW. This means the selected output becomes 0 (LOW) while all other outputs remain 1 (HIGH).

Why use NAND gates? NAND gates are universal gates and are often simpler and faster to manufacture in IC technology. Many real-world decoder ICs (like the 74138) use NAND gate outputs.

Exam Tip: If the question mentions “active low output” or “NAND gate decoder,” remember that the selected output goes to 0, not 1. This is a very common trick in exams!

2.3 Decoder Expansion – Building a 3×8 Decoder from Two 2×4 Decoders

Now, here is a very important exam topic. What if you need a 3-to-8 decoder but you only have 2-to-4 decoders? You can expand decoders by combining smaller ones. Let me show you how to build a 3×8 decoder using two 2×4 decoders.

The idea is simple. We have 3 inputs: A, B, C. The most significant bit (C) is used to select which of the two 2×4 decoders will be active. The lower two bits (A, B) go to both decoders as common inputs.

C (MSB) | +——-+——-+ | | Enable = 0 Enable = 1 | | +——+——+ +——+——+ | 2×4 Decoder | | 2×4 Decoder | | (Lower) | | (Upper) | +——+——+ +——+——+ Inputs: A, B Inputs: A, B Outputs: Outputs: D0, D1, D2, D3 D4, D5, D6, D7When C = 0: Lower decoder is active -> D0-D3 available When C = 1: Upper decoder is active -> D4-D7 available

Let me explain step by step:

Step 1: Connect input C directly to the Enable pin of the upper decoder and to the Enable pin of the lower decoder through a NOT gate (inverter).

Step 2: Connect inputs A and B to both decoders. Both decoders receive the same A and B inputs.

Step 3: When C = 0, the lower decoder is enabled (because its enable gets C’ = 1 after inversion… wait, let me be precise). Actually, when C = 0, we enable the lower decoder. When C = 1, we enable the upper decoder. The outputs D0–D3 come from the lower decoder, and D4–D7 come from the upper decoder.

Worked Example: What happens when input is CBA = 101?

  • C = 1, so the upper decoder is enabled, lower decoder is disabled.
  • A = 1, B = 0, so within the upper decoder, output line 1 (corresponding to BA = 01) is activated.
  • This gives us D4 + 1 = D5 = active output.
Important Formula for Decoder Expansion:
To build a larger decoder from smaller ones:
• Number of smaller decoders needed = \( \frac{2^n}{2^k} = 2^{n-k} \)
Where n = total input lines needed, k = input lines of each smaller decoder.

Example: 3×8 from 2×4 decoders: \( 2^{3-2} = 2^1 = 2 \) decoders needed.
Example: 4×16 from 2×4 decoders: \( 2^{4-2} = 2^2 = 4 \) decoders needed.
Example: 5×32 from 3×8 decoders: \( 2^{5-3} = 2^2 = 4 \) decoders needed.

Practice Questions – Decoder

Q1 (MCQ): A 3-to-8 line decoder has how many output lines?

(a) 3    (b) 8    (c) 6    (d) 11

Q2 (MCQ): In a NAND gate decoder with 3 inputs, when the input is 011, which output becomes active (LOW)?

(a) D0    (b) D2    (c) D3    (d) D6

Q3 (Workout): How many 3×8 decoders are needed to build a 5×32 decoder? Draw the connection approach in words.

Answer

Q1 Answer: (b) 8 — An n-to-2ⁿ decoder has 2ⁿ output lines. Here, 3-to-8 means 3 inputs and 2³ = 8 outputs. The formula \(2^n\) gives the number of outputs directly.

Q2 Answer: (c) D3 — The input 011 in binary equals 3 in decimal. In a NAND decoder, the selected output goes LOW (active low). So D3 becomes 0. Remember: NAND decoder = active LOW output.

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Q3 Answer: Using the formula: \(2^{n-k} = 2^{5-3} = 2^2 = 4\) decoders. We need four 3×8 decoders. The top 2 bits (of the 5 input bits) are connected to a 2×4 decoder (or logic gates) which generates 4 enable signals — one for each 3×8 decoder. The lower 3 bits are connected to all four 3×8 decoders as common inputs. When the top 2 bits select a particular decoder, the lower 3 bits determine which of its 8 outputs goes active.

3. Encoder

An Encoder does the exact opposite of what a decoder does. While a decoder converts binary input to one active output line, an encoder converts one active input line into a binary code at the output.

If a decoder is like a teacher calling a number and one student standing up, then an encoder is like one student raising a hand, and the system figuring out which number that student is.

The most common encoder is the 8-to-3 line encoder. It has 8 input lines and 3 output lines. When one of the 8 input lines is activated (set to 1), the encoder produces a 3-bit binary code at the output that represents which input line was activated.

Inputs Outputs D0 —-\ +—+ D1 —-+—[ENC]—| Y2 | D2 —-+ 8 to 3 | Y1 | D3 —-+ | Y0 | D4 —-+ +—+ D5 —-+ D6 —-+ D7 —-/Example: If D5 = 1 (all others 0) Output: Y2 Y1 Y0 = 1 0 1 (binary 5)

A special type of encoder called the priority encoder is very important for exams. In a priority encoder, if more than one input is active at the same time, the encoder gives priority to the input with the highest number and produces the binary code for that input only. This prevents confusion when multiple inputs are active.

Key Exam Note: Encoder = many inputs to few outputs (compresses). Decoder = few inputs to many outputs (expands). Priority encoder resolves conflicts by giving priority to the highest-numbered active input.

Practice Questions – Encoder

Q1 (MCQ): An 8-to-3 encoder has input D6 active. What is the output?

(a) 100    (b) 110    (c) 011    (d) 101

Q2 (True/False): A priority encoder can handle more than one active input at the same time.

Q3 (Short Answer): What is the main difference between a standard encoder and a priority encoder?

Answer

Q1 Answer: (b) 110 — Input D6 corresponds to decimal 6. The binary representation of 6 is 110. So Y2=1, Y1=1, Y0=0. The output is 110.

Q2 Answer: True — A priority encoder is specifically designed to handle situations where more than one input is active. It selects the highest-priority input and ignores the rest.

Q3 Answer: A standard encoder expects exactly one input to be active at a time. If multiple inputs are active, the output is undefined (invalid). A priority encoder solves this problem — when multiple inputs are active, it gives the output for the input with the highest priority (highest number). For example, if D3 and D6 are both active, the priority encoder outputs 110 (for D6), not 011.

4. Multiplexer (MUX)

A Multiplexer, often shortened to MUX, is a very important digital component. It is also called a data selector. A multiplexer selects one of several input lines and forwards the selected input to a single output line.

Think of a multiplexer like a television remote control. You have many channels (input lines), but you can only watch one channel at a time on your screen (output line). The channel number you press is the selection input that decides which channel reaches the screen.

A multiplexer has:

  • 2ⁿ data input lines (the channels to choose from)
  • n selection lines (to choose which input to send to output)
  • 1 output line (the selected data appears here)

The most common example is a 4-to-1 multiplexer. It has 4 data inputs (I0, I1, I2, I3), 2 selection lines (S1, S0), and 1 output (Y).

+——-+ I0 ——| | I1 ——| 4:1 |—— Y (Output) I2 ——| MUX | I3 ——| | +——-+ | | S1 +–+ S0 (Select Lines)S1 S0 | Output Y ——+———- 0 0 | I0 0 1 | I1 1 0 | I2 1 1 | I3

4.1 Boolean Function Implementation Using MUX

This is a very important exam topic. A multiplexer can be used to implement any Boolean function. Let me show you with a clear example.

Worked Example: Implement the function \( F(A,B,C) = \sum m(1, 3, 5, 6) \) using a 4-to-1 MUX.

Step 1: Write the truth table for the function:

ABCF
0000
0011
0100
0111
1000
1011
1101
1110

Step 2: Connect the first two variables (A, B) to the selection lines S1 and S0.

Step 3: For each combination of A and B, look at what C does to F, and connect the data input accordingly:

  • When A=0, B=0: F = 0 when C=0, F = 1 when C=1 → So I0 = C
  • When A=0, B=1: F = 0 when C=0, F = 1 when C=1 → So I1 = C
  • When A=1, B=0: F = 0 when C=0, F = 1 when C=1 → So I2 = C
  • When A=1, B=1: F = 1 when C=0, F = 0 when C=1 → So I3 = C’

Done! Connect I0=C, I1=C, I2=C, I3=C’ and the MUX implements the function.

Important Exam Formula – MUX Size for n Variables:
• To implement an n-variable function: use a \(2^{n-1}\)-to-1 MUX with n-1 variables on select lines and 1 variable on data inputs.
3 variables → 4-to-1 MUX (2 select lines + data inputs from 3rd variable)
4 variables → 8-to-1 MUX (3 select lines + data inputs from 4th variable)
2 variables → 2-to-1 MUX (1 select line + data inputs from 2nd variable)

Practice Questions – Multiplexer

Q1 (MCQ): A 8-to-1 multiplexer has how many selection lines?

(a) 2    (b) 3    (c) 4    (d) 8

Q2 (MCQ): To implement a 4-variable Boolean function using a MUX, what size MUX is needed?

(a) 4-to-1    (b) 8-to-1    (c) 16-to-1    (d) 2-to-1

Q3 (Workout): Implement \( F(A,B,C) = \sum m(0, 2, 4, 7) \) using a 4-to-1 MUX. Show what each data input should be connected to.

Answer

Q1 Answer: (b) 3 — The number of selection lines for a 2ⁿ-to-1 MUX is n. Here, 8 = 2³, so we need 3 selection lines.

Q2 Answer: (b) 8-to-1 — For n variables, we use a \(2^{n-1}\)-to-1 MUX. Here n = 4, so \(2^{4-1} = 2^3 = 8\). We need an 8-to-1 MUX.

Q3 Answer: Truth table for F(A,B,C) = Σm(0,2,4,7):

ABCF
0001
0010
0101
0110
1001
1010
1100
1111

Connect A and B to selection lines S1, S0:

  • AB=00: F follows C’=1, C=0 → I0 = C’
  • AB=01: F follows C’=1, C=0 → I1 = C’
  • AB=10: F follows C’=1, C=0 → I2 = C’
  • AB=11: F follows C’=0, C=1 → I3 = C

5. Registers

A register is a group of flip-flops. Each flip-flop can store one bit of information. So an n-bit register has n flip-flops and can store n bits of binary data. For example, a 4-bit register uses 4 flip-flops and can store a 4-bit number like 1011.

The simplest register is just a group of flip-flops with no extra gates. A clock input (C) loads all the inputs in parallel at the same time. But here is the catch — if you do not want to change the stored data, you must stop the clock. This is called inhibiting the clock.

5.1 Parallel Register with Load Control

A more practical register has a Load control input. This is much better because we do not need to stop the clock. The Load input decides whether new data enters the register or the old data stays:

  • Load = 1: New input data is transferred into the register (four inputs transfer in parallel)
  • Load = 0: Input is inhibited. The output is fed back to the input, so the current value stays the same (no change)
I0 –+–[LOAD]–D0–[FF0]– Q0 (Output) I1 –+–[LOAD]–D1–[FF1]– Q1 (Output) I2 –+–[LOAD]–D2–[FF2]– Q2 (Output) I3 –+–[LOAD]–D3–[FF3]– Q3 (Output)Load = 1: I0-I3 pass through to flip-flops (new data loaded) Load = 0: Q0-Q3 feedback to D0-D3 (old data kept)

The clock inputs always receive clock pulses. A buffer gate in the clock input increases the “fan-out” — meaning it can drive more circuits without weakening the signal.

5.2 Shift Register

A shift register is a register that can shift its binary information in one or both directions. The flip-flops are connected in a chain — the output of one flip-flop connects to the input of the next one.

Serial Input –> [FF0] –> [FF1] –> [FF2] –> [FF3] –> Serial OutputData enters from the left, moves right with each clock pulse. After 4 clock pulses, 4 bits have entered the register.

Key points about shift registers:

  • Data is input only to the leftmost flip-flop (for right-shift)
  • The serial input determines what goes into the leftmost position during each shift
  • The serial output is taken from the rightmost flip-flop
  • After n clock pulses, n bits have been serially loaded into an n-bit shift register

Worked Example: A 4-bit shift register initially contains 0000. The serial input receives the bits 1, 0, 1, 1 one by one. Show the register contents after each clock pulse.

Clock PulseSerial InputFF3FF2FF1FF0
Initial0000
111000
200100
311010
411101

After 4 pulses, the register holds 1101. Notice that the bits entered from the left and pushed the existing bits to the right. Also note that the bits appear in reverse order compared to how they were input — the first bit entered (1) is now at the rightmost position.

Practice Questions – Registers

Q1 (MCQ): How many flip-flops are required for a 6-bit register?

(a) 3    (b) 6    (c) 8    (d) 12

Q2 (MCQ): In a 4-bit parallel register with Load control, what happens when Load = 0?

(a) All flip-flops reset to 0    (b) New data is loaded    (c) Current data is maintained    (d) Data shifts right

Q3 (Workout): A 4-bit shift register contains 1010. The serial input is 0. Show the contents after 2 clock pulses.

Answer

Q1 Answer: (b) 6 — Each flip-flop stores exactly 1 bit. So for a 6-bit register, you need exactly 6 flip-flops. This is a direct relationship: n-bit register = n flip-flops.

Q2 Answer: (c) Current data is maintained — When Load = 0, the input is inhibited and the output feeds back to the input. This means the current value keeps cycling through the flip-flops unchanged. No new data enters, and data is not lost.

Q3 Answer:
Initial: FF3 FF2 FF1 FF0 = 1 0 1 0, Serial Input = 0
After Pulse 1: 0 shifts in from left → 0 1 0 1
After Pulse 2: 0 shifts in from left → 0 0 1 0
The register now contains 0010. Two bits (both 0s) have entered from the left, pushing the original bits to the right. The rightmost two original bits (1, 0) have been shifted out and lost.

6. Memory Unit

Memory is one of the most critical parts of any computer. In this section, we will cover the two main types of memory: RAM and ROM. Let me explain each one in detail.

6.1 RAM – Random Access Memory (Volatile)

RAM stands for Random Access Memory. It is called “random access” because you can access any memory location directly — you do not have to go through previous locations to reach a specific one. RAM is volatile, which means it loses all stored data when power is turned off.

Communication between memory and the rest of the system happens through three types of lines:

  • Data input and output lines — carry the actual data being read or written
  • Address selection lines — specify which memory location to access
  • Control lines — tell the memory what operation to perform (read or write)

Memory Write Operation

To write data into RAM, three steps are needed:

  1. Apply the binary address — specify WHERE to write
  2. Apply the data bits — specify WHAT to write
  3. Activate the write input — trigger the actual write operation

Memory Read Operation

To read data from RAM, two steps are needed:

  1. Apply the binary address — specify WHERE to read from
  2. Activate the read input — trigger the read operation, and the data appears on output lines
Important Exam Point: When you READ from memory, the content of the selected word does not change. Reading is a non-destructive operation. This is a very common exam question — students often mistakenly think reading erases data, but it does not!
+——————-+ Address Lines —>| | Data Input —>| RAM |—> Data Output Write Signal —>| (Memory Unit) | Read Signal —>| | +——————-+WRITE: Set Address + Set Data + Activate Write READ: Set Address + Activate Read (data appears at output)

6.2 ROM – Read Only Memory (Non-Volatile)

ROM stands for Read Only Memory. Unlike RAM, ROM is non-volatile — it keeps its data even when power is turned off. As the name suggests, you can only read from ROM; you cannot write new data into it during normal operation.

Here is a very important point that many students miss: ROM is classified as a combinational circuit, not a sequential circuit. Why? Because the outputs depend only on the present inputs (the address lines). There is no clock, no flip-flops, and no feedback. You give it an address, and it gives you the stored data. The output is a pure function of the input address.

Since ROM is combinational, there is no need for storage capabilities like in RAM. The data is physically built into the circuit during manufacturing (or programming).

ROM in Control Units

ROM plays a very important role in the design of control units for digital computers. A control unit that uses a ROM to store binary control information is called a microprogrammed control unit. The ROM stores microinstructions that tell the processor what control signals to generate for each machine instruction.

Important Points to Remember for Exam:
RAM = Volatile, supports both Read and Write
ROM = Non-volatile, Read only
RAM Read is non-destructive (data does not change)
ROM is a combinational circuit (output = function of address only)
Microprogrammed control uses ROM to store control information
• Memory Write: Address + Data + Write signal
• Memory Read: Address + Read signal (no data input needed)

Practice Questions – Memory

Q1 (MCQ): What happens to the data in a RAM location after a read operation?

(a) It is erased to zero    (b) It becomes complemented    (c) It remains unchanged    (d) It is shifted out

Q2 (MCQ): ROM is classified as a combinational circuit because:

(a) It uses flip-flops    (b) Its outputs depend only on present inputs    (c) It has a clock input    (d) It can be written to

Q3 (MCQ): A control unit that uses ROM to store binary control information is called:

(a) Hardwired control    (b) Microprogrammed control    (c) Sequential control    (d) Random control

Q4 (Fill in the Blank): The three types of lines used for communication between memory and its environment are ________ lines, ________ lines, and ________ lines.

Q5 (Short Answer): List the steps for a memory write operation and a memory read operation in RAM.

Answer

Q1 Answer: (c) It remains unchanged — Reading from RAM is a non-destructive operation. The data stays exactly as it was. This is a fundamental property of RAM that you must remember.

Q2 Answer: (b) Its outputs depend only on present inputs — The definition of a combinational circuit is that outputs depend only on present inputs, with no memory of past states. ROM fits this perfectly — give it an address (input), and it produces the stored data (output). No clock, no flip-flops, no state.

Q3 Answer: (b) Microprogrammed control — When a control unit uses ROM to store microinstructions (binary control information), it is called a microprogrammed control unit. This is in contrast to a hardwired control unit which uses combinational/sequential logic circuits instead of ROM.

Q4 Answer: Data input and output lines, Address selection lines, and Control lines.

Q5 Answer:
Memory Write: (1) Apply the binary address to specify the location. (2) Apply the data bits to specify what to store. (3) Activate the write input to perform the write.
Memory Read: (1) Apply the binary address to specify the location. (2) Activate the read input — the data at that location appears on the output lines. The stored data does not change.

Challenge Exam Questions – Chapter 3 (Hard Level)

These questions are designed to test your deep understanding. Try each one before checking the answer. Good luck, students!

Q1 (MCQ) – IC Classification

A digital component has 150 gates on a single chip. It is most accurately classified as:

(a) SSI device    (b) MSI device    (c) LSI device    (d) VLSI device

Answer: (b) MSI device
MSI devices contain 10 to 200 gates. Since 150 falls within this range, it is an MSI device. SSI is less than 10, LSI starts at 200, and VLSI is thousands. The boundary values are important — 200 is the dividing line between MSI and LSI.

Q2 (MCQ) – Logic Family Application

A designer is building a processor for a high-frequency trading system where speed is the top priority, regardless of power consumption. Which logic family should they choose?

(a) CMOS    (b) TTL    (c) ECL    (d) MOS

Answer: (c) ECL
ECL (Emitter-Coupled Logic) is the fastest logic family available. When the question emphasizes “speed is the top priority” or “high-speed operation,” ECL is always the answer. CMOS is for low power, MOS is for high density, and TTL is the standard general-purpose family.

Q3 (MCQ) – NAND Decoder

A 3-to-8 NAND gate decoder receives input 110. Which of the following statements is correct?

(a) D6 = 1, all others = 0    (b) D6 = 0, all others = 1    (c) D3 = 0, all others = 1    (d) D0 = 0, all others = 1

Answer: (b) D6 = 0, all others = 1
Input 110 in binary = decimal 6. In a NAND gate decoder, the output is active LOW. This means the selected output (D6) goes to 0, while all other outputs remain at 1. This is the opposite behavior of an AND gate decoder where D6 would be 1.

Q4 (MCQ) – Decoder Expansion

How many 2-to-4 line decoders are required to construct a 5-to-32 line decoder?

(a) 4    (b) 8    (c) 16    (d) 32

Q5 (MCQ) – MUX Function Implementation

A Boolean function F(A,B,C,D) has 4 variables. What is the minimum size of MUX needed to implement it?

(a) 4-to-1    (b) 8-to-1    (c) 16-to-1    (d) 2-to-1

Answer: (b) 8-to-1
For n variables, the minimum MUX size is \(2^{n-1}\)-to-1. Here n=4, so \(2^{4-1} = 2^3 = 8\). We use an 8-to-1 MUX with 3 variables on selection lines and the 4th variable (and its complement) connected to the data inputs as needed. A 16-to-1 MUX would also work but is not the minimum.

Q6 (True/False) – Register

In a parallel register with load control, the clock input must be inhibited to prevent data from changing when Load = 0.

Answer: False
This is the whole point of having a Load control input. When Load = 0, the output feeds back to the input through a feedback path, so the data recirculates and stays the same even though clock pulses continue to arrive. The clock does NOT need to be inhibited. Clock inhibition was needed only in the simplest registers that had NO load control.

Q7 (True/False) – ROM

ROM requires flip-flops for storing binary information internally.

Answer: False
ROM is a combinational circuit. It does not use flip-flops. The data in ROM is stored through the physical arrangement of the circuit (such as presence or absence of connections), not through clocked storage elements like flip-flops. Only sequential circuits like RAM registers need flip-flops.

Q8 (Fill in the Blank) – Multiple

(a) A group of flip-flops that stores binary information is called a ________.
(b) In a shift register, data enters from the ________ flip-flop and exits from the ________ flip-flop.
(c) ________ logic family is preferred for circuits needing high component density.
(d) A decoder with NAND gates produces ________ outputs.

Answer:
(a) Register — A register is defined as a group of flip-flops, with each flip-flop storing one bit.
(b) Leftmost, rightmost — In a right-shift register, serial input goes to the leftmost flip-flop, and serial output comes from the rightmost flip-flop.
(c) MOS — Metal-Oxide Semiconductor technology allows the highest component density (most gates per area).
(d) Active low — NAND gate decoders produce 0 on the selected output line and 1 on all others.

Q9 (Short Answer) – RAM vs ROM

Explain three differences between RAM and ROM based on the concepts covered in this chapter.

Answer:
1. Volatility: RAM is volatile (loses data when power is off). ROM is non-volatile (retains data without power).
2. Read/Write Capability: RAM supports both read and write operations. ROM supports only read operations during normal use.
3. Circuit Classification: RAM uses flip-flops or storage cells and is a sequential circuit. ROM is a combinational circuit because its outputs depend only on the present address inputs.
Additional point: ROM is used in microprogrammed control units to store binary control information, while RAM is used for general data storage during program execution.

Q10 (Step-by-Step Calculation) – Shift Register

A 4-bit right-shift register initially contains 1100. Bits are fed in from the serial input in this order: 1, 0, 1. Show the register contents after each clock pulse. What is the serial output bit after each pulse?

Answer:
After PulseSerial InputFF3FF2FF1FF0Serial Output (from FF0)
Initial1100
1111100 (first bit shifted out)
2001110 (second bit shifted out)
3110111 (third bit shifted out)
After 3 pulses, the register contains 1011. The serial output bits in order were: 0, 0, 1. Notice how each clock pulse shifts everything one position to the right, the serial input enters from the left, and the rightmost bit falls out as serial output.

Q11 (Step-by-Step Calculation) – MUX Implementation

Implement the function \( F(x,y,z) = x’yz + xy’z’ + xyz \) using a 4-to-1 multiplexer. Show all data input connections clearly.

Answer:
Step 1: Create the truth table:
xyzF
0000
0010
0100
0111 (x’yz)
1001 (xy’z’)
1010
1100
1111 (xyz)
Step 2: Connect x, y to selection lines S1, S0. Analyze each pair:
• xy = 00: F = 0 for z=0, F = 0 for z=1 → I0 = 0
• xy = 01: F = 0 for z=0, F = 1 for z=1 → I1 = z
• xy = 10: F = 1 for z=0, F = 0 for z=1 → I2 = z’
• xy = 11: F = 0 for z=0, F = 1 for z=1 → I3 = z
Final connection: I0 = 0, I1 = z, I2 = z’, I3 = z. Select lines: S1=x, S0=y.

Q12 (MCQ) – Memory Operations

During a memory read operation in RAM, which of the following is NOT required?

(a) Address lines    (b) Read control signal    (c) Data input lines    (d) Data output lines

Answer: (c) Data input lines
During a read operation, you only need to specify the address and activate the read signal. The data then appears on the output lines. Data input lines are only needed during a WRITE operation (you need to provide the data to write). This is a common trick question — students often confuse read and write requirements.

Q13 (Short Answer) – Buffer Gate in Register

What is the purpose of the buffer gate in the clock input of a parallel register? Explain the term “fan-out” in this context.

Answer:
A buffer gate is placed in the clock input line to increase the fan-out of the clock signal. Fan-out refers to the number of gate inputs that a single output can drive without the signal becoming too weak. In a register with multiple flip-flops, the clock signal needs to reach all flip-flops simultaneously. Without a buffer, driving multiple flip-flop clock inputs from one source might weaken the signal. The buffer strengthens the clock signal so it can properly drive all flip-flops in the register.

Q14 (MCQ) – Encoder

In a priority encoder with 8 inputs, if inputs D2, D5, and D7 are all active simultaneously, what is the output?

(a) 010    (b) 101    (c) 111    (d) 001

Answer: (c) 111
A priority encoder gives priority to the highest-numbered active input. Among D2, D5, and D7, the highest is D7. The binary code for 7 is 111. So the output is 111, regardless of the other active inputs. The priority encoder essentially “ignores” D2 and D5 because D7 has higher priority.

Q15 (Workout) – Decoder with Enable

A 2-to-4 decoder has an active-HIGH enable input E. Inputs are A and B. The decoder uses AND gates. Write the Boolean expression for each output (D0, D1, D2, D3) in terms of E, A, and B. If E = 0, what are all outputs?

Answer:
The enable input E is ANDed with each output:
\[ D_0 = E \cdot A’ \cdot B’ \] \[ D_1 = E \cdot A’ \cdot B \] \[ D_2 = E \cdot A \cdot B’ \] \[ D_3 = E \cdot A \cdot B \]
When E = 0: Every output becomes 0 regardless of A and B values. This is because E = 0 forces the AND gate output to 0 for all four outputs. The decoder is effectively “turned off” — no output is selected. Only when E = 1 does the decoder function normally, activating one output based on A and B.

Quick Revision Sheet – Chapter 3

Use this sheet for fast revision before your exam. All key facts in one place!

IC Integration Levels

LevelGatesTypical Components
SSI< 10Basic gates
MSI10–200Decoders, Encoders, Adders, Registers
LSI200–few thousandProcessors
VLSIThousands+Memory arrays, Microcomputer chips

Logic Families at a Glance

FamilyKey FeatureBest For
TTLStandardGeneral purpose
ECLFastestHigh-speed systems
MOSHigh densityCircuits needing many components
CMOSLow powerBattery-operated devices

Decoder Key Facts

  • n inputs → \(2^n\) outputs
  • AND decoder: selected output = 1 (active HIGH)
  • NAND decoder: selected output = 0 (active LOW)
  • Expansion formula: \(2^{n-k}\) smaller decoders needed

Encoder Key Facts

  • \(2^n\) inputs → n outputs (opposite of decoder)
  • Priority encoder: gives output for highest-numbered active input

Multiplexer Key Facts

  • \(2^n\) data inputs + n select lines → 1 output
  • Also called data selector
  • n-variable function → use \(2^{n-1}\)-to-1 MUX

Register Key Facts

  • n-bit register = n flip-flops
  • Parallel register: Load=1 → new data; Load=0 → feedback (no change)
  • Shift register: chain of flip-flops, data enters leftmost, exits rightmost
  • Buffer gate in clock = increases fan-out

Memory Key Facts

PropertyRAMROM
VolatilityVolatileNon-volatile
OperationsRead + WriteRead only
Circuit typeSequentialCombinational
Read destroys data?NoNo
Used inGeneral data storageMicroprogrammed control

RAM Operations

  • Write: Address + Data + Write signal
  • Read: Address + Read signal (data unchanged after read)

Quick Formulas

\[ \text{Decoder outputs} = 2^n \quad | \quad \text{MUX select lines} = n \text{ for } 2^n\text{-to-1 MUX} \] \[ \text{MUX for n-variable function} = 2^{n-1}\text{-to-1} \quad | \quad \text{Decoders for expansion} = 2^{n-k} \] \[ \text{n-bit register} = n \text{ flip-flops} \quad | \quad \text{Shift register serial load time} = n \text{ clock pulses} \]
Last Minute Exam Tips:
• Never say “reading RAM destroys data” — it does NOT!
• Never say “ROM is sequential” — it is COMBINATIONAL!
• NAND decoder = active LOW (selected output = 0)
• ECL = speed king, CMOS = power saver
• When asked about “microprogrammed control” — answer always involves ROM
• Count gates carefully for SSI/MSI/LSI/VLSI questions — the boundary numbers matter!

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