Hello, dear students! Welcome to your first lesson in Computer Organization and Architecture (COA). Today, we are going to build a very strong foundation. This topic is the starting point of the entire course, so please read every part carefully. I will explain each concept in a simple way so you can understand it easily and score well in your exam. Are you ready? Let’s begin!
Before we go deep, let me ask you: Have you ever wondered what happens inside your computer when you click something? That is exactly what this course is about. We will learn how a computer is built, how its parts work together, and how instructions are processed. This lesson covers the basic building blocks — from the high-level architecture down to logic gates and flip-flops.
1. Computer Architecture
Let me start by asking you a question: What is Computer Architecture? Well, computer architecture is concerned with the structure and behavior of the various functional modules of a computer system. When we design a computer system, the architecture is designed first, before anything else.
Think of it like this — before a house is built, an architect draws a plan. That plan shows what rooms the house will have, where doors and windows will be, and how the house will look from outside. In the same way, Computer Architecture is the “plan” of the computer. It specifies:
- The instruction set — what operations the computer can perform
- The hardware units that implement those instructions
- How hardware and software interact with each other
So, architecture acts as the interface between hardware and software. It is what a programmer sees when they write code. A programmer views the architecture in terms of instructions, addressing modes, and registers.
Computer architecture deals with high-level design issues. It helps us understand the functionalities of a system without worrying about how each part is physically built. Let me give you a simple example: When you write C = A + B in a program, the architecture defines that there is an ADD instruction available, what registers you can use, and how data can be addressed. It does NOT tell you how the addition circuit is built with transistors — that part belongs to organization.
Computer Architecture involves Logic aspects:
• Instruction sets — the set of all operations a CPU can perform
• Addressing modes — ways to specify the address of data
• Data types — types of data the computer can handle (integer, float, etc.)
• Cache optimization — strategies to make cache memory efficient
📝 Practice Questions — Computer Architecture
Q1 (MCQ): Which of the following is NOT a concern of Computer Architecture?
A) Instruction set design B) Addressing modes C) Circuit design of adders D) Data types
Explanation: Circuit design of adders is a low-level design issue that falls under Computer Organization, not Architecture. Architecture deals with high-level design like instruction sets, addressing modes, data types, and cache optimization. The circuit-level implementation of an adder is about how hardware components are physically connected, which is organization.
Q2 (MCQ): Computer architecture acts as the interface between:
A) Input and Output B) Hardware and Software C) CPU and Memory D) ALU and Control Unit
Explanation: According to the PDF, computer architecture acts as the interface between hardware and software. It defines what the programmer sees (software view) and what the hardware provides. This is a very common exam question!
Q3 (Write/Explain): List and briefly explain the four logical aspects involved in Computer Architecture.
1. Instruction sets — The complete set of operations/machine instructions that a CPU can execute.
2. Addressing modes — The different ways of specifying the address of an operand in an instruction.
3. Data types — The types of data the computer can handle, such as integers, floating-point numbers, and characters.
4. Cache optimization — Techniques and strategies used to improve the performance of cache memory in the system.
2. Computer Organization
Now, let’s move to the next important concept. If architecture is the plan of the house, then organization is how the house is actually built — which materials are used, how bricks are laid, where the plumbing pipes go, and so on. Let me explain this properly.
Computer Organization is concerned with how hardware components are connected together to form a computer system. It describes the functions of the various units of a digital system and deals with the components of a connection in a system.
It tells us how exactly all the units in the system are arranged and interconnected. So while architecture tells us WHAT the computer does, organization tells us HOW it does it. Organization expresses the realization of architecture. An organization is done on the basis of architecture.
Computer Organization deals with low-level design issues. Let me make this very clear with an example. The architecture says “the computer has an ADD instruction.” The organization tells us whether that addition is done using a ripple-carry adder, a carry-lookahead adder, or some other circuit. The architecture doesn’t change — but the organization can change between different models of the same computer family.
Now, do you remember the five main components of a computer? A computer consists of five main components, namely:
- Input Unit — Takes data from the outside world (keyboard, mouse, etc.)
- Memory Unit — Stores data and instructions
- Central Processing Unit (CPU) — Processes data
- Arithmetic & Logical Unit (ALU) — Performs arithmetic and logical operations
- Control Unit — Directs and coordinates all operations
- Output Unit — Sends processed results to the outside world (monitor, printer, etc.)
Computer Organization involves Physical Components:
• Circuit design — designing the actual electronic circuits
• Adders — hardware circuits for addition (ripple-carry, carry-lookahead)
• Signals — control signals, clock signals, data signals
• Peripherals — I/O devices and their interfaces
📝 Practice Questions — Computer Organization
Q1 (MCQ): Which of the following is a concern of Computer Organization rather than Computer Architecture?
A) Instruction set B) Addressing modes C) Hardware signal design D) Data types
Explanation: Hardware signal design is a physical/low-level concern that belongs to Computer Organization. Instruction set, addressing modes, and data types are all high-level logical concerns that belong to Computer Architecture.
Q2 (MCQ): “Organization expresses the realization of architecture.” This statement means:
A) Architecture is built from organization B) Organization implements what architecture specifies C) Both are the same thing D) Organization is designed before architecture
Explanation: Architecture specifies WHAT the computer should do (instruction set, registers, etc.), and organization is the actual physical implementation of that specification. Architecture is designed first, then organization follows. They are NOT the same thing.
Q3 (List and Explain): List the five main components of a computer system as described in Computer Organization.
1. Input Unit — Accepts data from external sources and converts it into a form the computer can understand.
2. Memory Unit — Stores data, instructions, and intermediate results.
3. Central Processing Unit (CPU) — The brain of the computer that processes all data and instructions.
4. Arithmetic & Logical Unit (ALU) — Performs all arithmetic calculations (add, subtract, etc.) and logical operations (AND, OR, NOT, etc.).
5. Control Unit — Generates control signals to direct and coordinate the operations of all other units.
6. Output Unit — Converts processed data into human-readable form and delivers it to the user.
3. Logic Gates
Now we are entering a very important section. Logic gates are the main structural part of a digital system. Every digital computer, no matter how complex, is built from these basic gates. So please pay close attention — this is a guaranteed exam topic!
What is a logic gate? A logic gate is a block of hardware that produces signals of binary 1 or 0 when input logic requirements are satisfied. Each gate has a distinct graphic symbol, and its operation can be described by means of algebraic expressions.
The seven basic logic gates are: AND, OR, XOR, NOT, NAND, NOR, and XNOR.
Here is a key point: The relationship between the input-output binary variables for each gate can be represented in tabular form by a truth table. Each gate has one or two binary input variables (designated by A and B) and one binary output variable (designated by x). Binary number 1 represents HIGH and 0 represents LOW.
Let me now explain each gate one by one with its truth table and operation. Ready? Let’s go!
3.1 AND Gate
The AND gate is an electronic circuit which gives a high output (1) only if ALL its inputs are high. If even one input is low (0), the output will be low. Think of it like a series of switches — all switches must be ON for the current to flow.
The AND operation is represented by a dot (.) sign. So, the expression is:
| A | B | x = A · B |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
3.2 OR Gate
The OR gate gives a high output (1) if one OR more of its inputs are high. Even if just one input is 1, the output becomes 1. The output is 0 only when ALL inputs are 0.
The OR operation is represented by a plus (+) sign:
| A | B | x = A + B |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 1 |
3.3 NOT Gate
The NOT gate produces an inverted version of the input at its output. A low input (0) produces a high output (1), and a high input (1) produces a low output (0). That is why it is also called an Inverter.
Or sometimes written as:
| A | x = A’ |
|---|---|
| 0 | 1 |
| 1 | 0 |
3.4 NAND Gate
The NAND gate stands for NOT-AND. It is equal to an AND gate followed by a NOT gate. So, you first perform the AND operation, then invert the result. The NAND gate gives a high output (1) if ANY of the inputs are low (0). The output is 0 only when ALL inputs are 1.
| A | B | x = (A · B)’ |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
The NAND gate is represented by an AND gate with a small circle on the output. That small circle represents inversion (NOT operation).
3.5 NOR Gate
The NOR gate stands for NOT-OR. It is equal to an OR gate followed by a NOT gate. The NOR gate gives a low output (0) if ANY of the inputs are high (1). The output is 1 only when ALL inputs are 0.
| A | B | x = (A + B)’ |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 0 |
Like NAND, the NOR gate is represented by an OR gate with a small circle on the output representing inversion.
3.6 XOR Gate (Exclusive-OR)
The XOR gate gives a high output (1) if one of its inputs is high but NOT both. In other words, the output is 1 when the inputs are different. The XOR operation is represented by an encircled plus sign (⊕).
| A | B | x = A ⊕ B |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
3.7 XNOR Gate (Exclusive-NOR)
The XNOR gate does the inverse operation of the XOR gate. It gives a low output (0) if one of its inputs is high but not both. In other words, the output is 1 when the inputs are the same. That is why it is also called the Equivalence gate.
| A | B | x = (A ⊕ B)’ |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
• AND: Output 1 only when ALL inputs are 1 → \(x = A \cdot B\)
• OR: Output 1 when ANY input is 1 → \(x = A + B\)
• NOT: Inverts input → \(x = A’\)
• NAND: NOT of AND → \(x = (A \cdot B)’\)
• NOR: NOT of OR → \(x = (A + B)’\)
• XOR: Output 1 when inputs DIFFER → \(x = A \oplus B\)
• XNOR: Output 1 when inputs SAME → \(x = (A \oplus B)’\)
📝 Practice Questions — Logic Gates
Q1 (MCQ): A logic gate produces output 1 only when both inputs are 1. This gate is:
A) OR B) NAND C) AND D) XOR
Explanation: The AND gate gives output 1 only if ALL inputs are high (1). OR gives 1 if any input is 1, NAND gives 0 when all inputs are 1, and XOR gives 1 when inputs are different.
Q2 (MCQ): The output of a NOR gate is 1 when:
A) Any input is 1 B) All inputs are 1 C) All inputs are 0 D) One input is 0 and other is 1
Explanation: NOR gate = NOT of OR. OR gives 1 when any input is 1, so NOT of that gives 0 when any input is 1. NOR gives 1 only when ALL inputs are 0 (since 0+0=0, and NOT of 0 = 1).
Q3 (MCQ): Which gate is known as the Equivalence gate?
A) XOR B) XNOR C) NAND D) NOR
Explanation: The XNOR gate is also called the Equivalence gate because it produces output 1 when both inputs are the same (both 0 or both 1), meaning the inputs are “equivalent.”
Q4 (Workout): If A = 1, B = 0, and C = 1, find the output of: \(x = (A \cdot B)’ + C\)
Step 1: Find \(A \cdot B = 1 \cdot 0 = 0\)
Step 2: Find \((A \cdot B)’ = 0′ = 1\) (NAND operation)
Step 3: Find \(1 + C = 1 + 1 = 1\) (OR operation)
Final output: x = 1
4. Boolean Algebra
Now let’s talk about Boolean algebra. Can you guess why it is important? Yes — because Boolean algebra is the mathematical foundation of all digital logic circuits. Every logic gate operation we just studied can be expressed using Boolean algebra.
Boolean algebra can be considered as an algebra that deals with binary variables and logic operations. The variables are designated by letters such as A, B, x, and y. The basic operations performed are AND, OR, and complement (NOT).
The Boolean algebraic functions are mostly expressed with binary variables, logic operation symbols, parentheses, and equal sign. For a given value of variables, the Boolean function can be either 1 or 0.
Let me explain with a very important example from your PDF:
4.1 Example: Boolean Function \(F = x + y’z\)
Consider the Boolean function:
Let me break this down step by step so you understand it completely:
- y’ means the complement (NOT) of y
- y’z means y’ AND z (the dot is implied)
- x + y’z means x OR (y’z)
How to convert this into a logic diagram? The Boolean function is transformed from an algebraic expression into a logic diagram composed of AND, OR, and inverter gates:
- An inverter (NOT gate) at input ‘y’ generates its complement y’
- An AND gate is used for the term y’z (takes y’ and z as inputs)
- An OR gate combines the two terms (x and y’z)
The variables of the function (x, y, z) are taken as the inputs of the circuit, and the function symbol (F) is taken as the output of the circuit.
4.2 Truth Table for \(F = x + y’z\)
To represent this function in a truth table, we need a list of the 2n combinations of n binary variables. Here we have 3 variables (x, y, z), so we need 23 = 8 rows.
| x | y | z | y’ | y’z | F = x + y’z |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 1 | 0 | 0 |
| 0 | 0 | 1 | 1 | 1 | 1 |
| 0 | 1 | 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 | 0 | 0 |
| 1 | 0 | 0 | 1 | 0 | 1 |
| 1 | 0 | 1 | 1 | 1 | 1 |
| 1 | 1 | 0 | 0 | 0 | 1 |
| 1 | 1 | 1 | 0 | 0 | 1 |
Let me explain a few rows so you understand the method:
- Row 1 (x=0, y=0, z=0): y’ = 1, y’z = 1·0 = 0, F = 0 + 0 = 0
- Row 2 (x=0, y=0, z=1): y’ = 1, y’z = 1·1 = 1, F = 0 + 1 = 1
- Row 5 (x=1, y=0, z=0): y’ = 1, y’z = 1·0 = 0, F = 1 + 0 = 1
- Row 7 (x=1, y=1, z=0): y’ = 0, y’z = 0·0 = 0, F = 1 + 0 = 1
📝 Practice Questions — Boolean Algebra
Q1 (MCQ): For the Boolean function \(F = x + y’z\), what is the output when x = 0, y = 1, z = 1?
A) 0 B) 1 C) Undefined D) Depends on circuit
Explanation: y’ = 1′ = 0, y’z = 0·1 = 0, F = 0 + 0 = 0. This corresponds to Row 4 of the truth table. Many students make the mistake of forgetting to complement y first!
Q2 (MCQ): How many rows are required in a truth table for a Boolean function with 4 variables?
A) 8 B) 16 C) 32 D) 4
Explanation: The number of rows in a truth table = 2n, where n is the number of variables. For 4 variables: 24 = 16 rows. Formula: Rows = 2n
Q3 (Workout): Draw the logic diagram and construct the truth table for the Boolean function \(F = A’B + AC\).
Logic Diagram:
• NOT gate on A → produces A’
• AND gate with inputs A’ and B → produces A’B
• AND gate with inputs A and C → produces AC
• OR gate combines A’B and AC → produces F
Truth Table (23 = 8 rows):
| A | B | C | A’ | A’B | AC | F = A’B + AC |
|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 1 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 |
| 0 | 1 | 0 | 1 | 1 | 0 | 1 |
| 0 | 1 | 1 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 |
| 1 | 0 | 1 | 0 | 0 | 1 | 1 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 |
| 1 | 1 | 1 | 0 | 0 | 1 | 1 |
5. Combinational Circuits
Now we are moving to a very important topic. Have you heard the term “combinational circuit” before? Let me explain it in a simple way. A combinational circuit comprises of logic gates whose outputs at any time are determined directly from the present combination of inputs without any regard to previous inputs.
Read that definition again carefully. The key phrase is “without any regard to previous inputs”. This means the output depends ONLY on what inputs are right now — it has no memory of what happened before. This is what makes it different from sequential circuits (which use flip-flops and have memory).
A combinational circuit performs a specific information-processing operation fully specified logically by a set of Boolean functions. The basic components are:
- n input variables — come from an external source
- Logic gates — process the inputs
- m output variables — go to an external destination
In many applications, the source or destination are storage registers.
5.1 Design Procedure of a Combinational Circuit
This is a very exam-relevant topic. The design procedure involves the following steps — memorize these steps!
- The problem is stated — understand what the circuit should do
- Determine the number of input and output variables — count available inputs and required outputs
- Allocate letter symbols — assign letters to input and output variables
- Derive the truth table — define the exact relationship between inputs and outputs
- Obtain simplified Boolean functions — simplify each output function (using K-map or algebraic method)
- Draw the logic diagram — convert Boolean functions into a gate-level circuit diagram
5.2 Half Adder
Now let’s apply the design procedure to build a Half Adder. The combinational circuit that performs the addition of two bits is called a half adder.
A Half-adder circuit needs two binary inputs and two binary outputs. The input variables show the augend and addend bits whereas the output variables produce the sum and carry.
Step 1 & 2: Problem is to add two bits. Two inputs, two outputs.
Step 3: Inputs: x, y. Outputs: S (Sum), C (Carry).
Step 4: Truth table:
| x | y | S (Sum) | C (Carry) |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
Notice that the Carry output is 0 unless both inputs are 1. The Sum (S) represents the least significant bit of the sum.
Step 5: Simplified Boolean functions from the truth table:
Look at this carefully. The Sum is the XOR of the inputs, and the Carry is the AND of the inputs. These are the simplified SOP (Sum of Products) expressions.
Step 6: Logic diagram:
• Sum: \(S = x \oplus y\) (XOR gate)
• Carry: \(C = x \cdot y\) (AND gate)
• Inputs: 2 (x, y) | Outputs: 2 (S, C)
• Limitation: Cannot accept a carry from a previous stage — that’s why it’s called “half”
5.3 Full Adder
Now, can you guess what a Full Adder does differently? A full adder performs the addition of three bits — two significant bits and a previous carry. This solves the limitation of the half adder!
This circuit needs three binary inputs and two binary outputs.
- x and y — the two significant bits to be added
- z — the carry from the previous lower significant position
- S — Sum output
- C — Carry output
The eight rows under the input variables designate all possible combinations of 0’s and 1’s that these three variables may have (23 = 8 rows).
| x | y | z | S (Sum) | C (Carry) |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 | 1 |
| 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 | 1 |
Each output Boolean function can be simplified by using a unique map method (K-map). The simplified Boolean functions are:
Notice that the Sum is now a three-variable XOR operation, and the Carry is a more complex expression involving three AND terms combined with OR.
• Sum: \(S = x \oplus y \oplus z\) (Two XOR gates in cascade)
• Carry: \(C = xy + xz + yz\) (Three AND gates + one OR gate)
• Inputs: 3 (x, y, z) | Outputs: 2 (S, C)
• Key difference from Half Adder: Full Adder accepts a carry input (z) from the previous stage
• Half Adder: 2 inputs, 2 outputs, no carry input
• Full Adder: 3 inputs, 2 outputs, has carry input from previous stage
• A Full Adder can be built using two Half Adders — this is a very common exam question!
📝 Practice Questions — Combinational Circuits
Q1 (MCQ): The Sum output of a Half Adder is obtained using which gate?
A) AND B) OR C) XOR D) NAND
Explanation: The Sum of a Half Adder is given by \(S = x \oplus y\), which is the XOR gate. The Carry is obtained using the AND gate (\(C = x \cdot y\)). This is a very basic but frequently asked question!
Q2 (MCQ): A Full Adder has how many input variables?
A) 2 B) 3 C) 4 D) 5
Explanation: A Full Adder has 3 input variables: two significant bits (x and y) and one carry bit (z) from the previous lower significant position. A Half Adder has only 2 inputs.
Q3 (MCQ): The carry output of a Full Adder is given by:
A) \(x \oplus y \oplus z\) B) \(xy + xz + yz\) C) \(x \cdot y\) D) \(x + y + z\)
Explanation: The carry of a Full Adder is \(C = xy + xz + yz\). Option A is the Sum expression. Option C is the carry of a Half Adder (not Full Adder). Option D is a simple OR which is incorrect.
Q4 (Workout): Design a Half Adder circuit. Write the truth table, derive Boolean expressions, and draw the logic diagram.
Step 1: Problem — Add two bits
Step 2: 2 inputs (x, y), 2 outputs (S, C)
Step 3: Variables assigned
Step 4: Truth Table:
| x | y | S | C |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
• S = 1 when inputs are different → \(S = x \oplus y\)
• C = 1 only when both inputs are 1 → \(C = x \cdot y\)
Step 6: Logic diagram uses one XOR gate (for S) and one AND gate (for C), both taking x and y as inputs.
Q5 (List and Explain): List the six steps in the design procedure of a combinational circuit.
1. The problem is stated — Clearly define what the circuit should accomplish.
2. Determine the number of variables — Count the available input variables and required output variables.
3. Allocate letter symbols — Assign letter symbols to each input and output variable.
4. Derive the truth table — Create a truth table that defines the exact relationship between every combination of inputs and outputs.
5. Obtain simplified Boolean functions — Simplify each output function using methods like Karnaugh maps or Boolean algebra theorems.
6. Draw the logic diagram — Convert the simplified Boolean expressions into a circuit diagram using appropriate logic gates.
6. Flip-Flops
Now we enter a completely different world! So far, we studied combinational circuits — circuits with no memory. But a computer needs memory to store data. That’s where flip-flops come in!
Flip-flops are an application of logic gates. A flip-flop circuit can remain in a binary state indefinitely (as long as power is delivered to the circuit) until directed by an input signal to switch states. This ability to “hold” a state is what gives flip-flops their memory property. They are the basic building blocks of sequential circuits.
Let me explain each type of flip-flop one by one. Pay close attention — there are four main types and exam questions come from each one!
6.1 S-R Flip-Flop (Basic Flip-Flop)
S-R flip-flop stands for SET-RESET flip-flop. It consists of two NOR gates (or two NAND gates) connected in a cross-coupled manner. These flip-flops are also called S-R Latch.
The S-R flip-flop has:
- Two inputs: SET [S] and RESET [R]
- Two outputs: Q and Q’ (Q’ is always the complement of Q)
| S | R | Q (Output) | Action |
|---|---|---|---|
| 0 | 0 | Previous state | No change (Hold) |
| 0 | 1 | 0 | Reset |
| 1 | 0 | 1 | Set |
| 1 | 1 | ? | Invalid (Forbidden) |
6.2 Clocked S-R Flip-Flop
The basic S-R flip-flop has a problem — it changes state whenever inputs change, without any control. To solve this, a clock pulse is added. The clock determines when the state of the circuit is to be changed.
A clock pulse is given to the inputs of the AND gates. If the value of the clock pulse is 0, the outputs of both AND gates remain 0, meaning no change occurs regardless of S and R values. Only when the clock pulse is 1, the S and R inputs can affect the flip-flop.
The limitation with S-R flip-flop using NOR and NAND gates (the invalid state when S=1, R=1) can be overcome by using a stable SR flip-flop that can handle certain invalid states, regardless of the condition of either the Set or the Reset inputs.
6.3 D Flip-Flop
The D flip-flop is a slight modification of the clocked SR flip-flop. The main purpose of the D flip-flop is to eliminate the invalid state problem of the S-R flip-flop.
How? The D input is connected to the S input, and the complement of D is connected to the R input. This means S and R can never be the same — if D = 0, then S = 0 and R = 1; if D = 1, then S = 1 and R = 0. The invalid state (S=1, R=1) is impossible!
| D (Input) | Q (Output) | Action |
|---|---|---|
| 0 | 0 | CLEAR (Reset) |
| 1 | 1 | SET |
When the clock pulse (CP) value is 1 (HIGH), the flip-flop moves to the SET state if D = 1. If D = 0 (LOW), the flip-flop switches to the CLEAR state.
6.4 J-K Flip-Flop
The J-K flip-flop can be considered as a modification of the S-R flip-flop. The main difference is that the intermediate state (invalid state) is more refined and precise than that of an S-R flip-flop.
The characteristics of inputs ‘J’ and ‘K’ are the same as the ‘S’ and ‘R’ inputs of the S-R flip-flop:
- J stands for SET (like S in S-R)
- K stands for CLEAR (like R in S-R)
| J | K | Q (Output) | Action |
|---|---|---|---|
| 0 | 0 | Previous state | No change |
| 0 | 1 | 0 | Reset |
| 1 | 0 | 1 | Set |
| 1 | 1 | Complement | Toggle |
Now, here is the most important difference! When both inputs J and K are HIGH (1), instead of going to an invalid state like the S-R flip-flop, the J-K flip-flop switches to the complement state. This is called toggling. So, if Q = 1, it switches to Q = 0, and if Q = 0, it switches to Q = 1.
6.5 T Flip-Flop
The T flip-flop is a much simpler version of the J-K flip-flop. Both the J and K inputs are connected together as a single input called T (Toggle). That is why it is also called a single-input J-K flip-flop.
| T (Input) | Q (Output) | Action |
|---|---|---|
| 0 | Previous state | No change (Hold) |
| 1 | Complement | Toggle |
When T = 0, the flip-flop holds its current state. When T = 1, the flip-flop toggles (switches to the opposite state). The T flip-flop is very useful in counters and frequency dividers.
| Flip-Flop | Inputs | Invalid State? | Special Feature |
|---|---|---|---|
| S-R | S, R | Yes (S=1, R=1) | Basic latch |
| Clocked S-R | S, R, Clock | Yes (S=1, R=1) | Clock-controlled |
| D | D, Clock | No | Output follows D input |
| J-K | J, K, Clock | No | Toggles when J=K=1 |
| T | T, Clock | No | Toggles when T=1 |
📝 Practice Questions — Flip-Flops
Q1 (MCQ): Which flip-flop has an invalid/forbidden state?
A) D flip-flop B) J-K flip-flop C) T flip-flop D) S-R flip-flop
Explanation: The S-R flip-flop has an invalid state when S = 1 and R = 1. The D, J-K, and T flip-flops were all designed to eliminate this problem. The J-K flip-flop converts this condition into a toggle operation.
Q2 (MCQ): When J = 1 and K = 1 in a J-K flip-flop, the output will:
A) Set to 1 B) Reset to 0 C) Toggle to complement state D) Remain unchanged
Explanation: Unlike the S-R flip-flop which goes to an invalid state when both inputs are 1, the J-K flip-flop toggles — it switches to the complement of its current state. If Q was 1, it becomes 0, and if Q was 0, it becomes 1.
Q3 (MCQ): The D flip-flop is a modification of which flip-flop?
A) T flip-flop B) J-K flip-flop C) Clocked S-R flip-flop D) None of the above
Explanation: According to the PDF, the D flip-flop is a “slight modification of clocked SR flip-flop.” The D input connects to S, and D’ connects to R, making the invalid state impossible.
Q4 (MCQ): A T flip-flop is also known as:
A) Dual-input J-K flip-flop B) Single-input J-K flip-flop C) Modified D flip-flop D) Basic S-R latch
Explanation: The T flip-flop is formed by connecting both J and K inputs of a J-K flip-flop together as a single input (T). That is why it is called a “single-input J-K flip-flop.”
Q5 (Write/Explain): Explain how the D flip-flop eliminates the invalid state problem of the S-R flip-flop.
• When D = 0: S = 0 and R = 1 (Reset state — valid)
• When D = 1: S = 1 and R = 0 (Set state — valid)
Since S and R are always complements of each other, the condition S = 1, R = 1 (invalid state) can never occur. This completely eliminates the invalid state problem of the S-R flip-flop.
7. Triggering of Flip-Flops
Let me ask you: how does a flip-flop actually change its state? The state of a flip-flop is changed by a momentary change in the input signal. This momentary change is known as a Trigger, and the transition it causes is said to be triggering the flip-flop.
Pulses trigger clocked flip-flops. A pulse starts from the initial value of 0, goes momentarily to 1, and after a short while, returns to its initial 0 value.
A clock pulse is either positive or negative:
- Positive clock source: remains at 0 during the interval between pulses and goes to 1 during the occurrence of a pulse
- Negative clock source: remains at 1 during the interval between pulses and goes to 0 during the occurrence of a pulse
The pulse goes through two signal transitions: from 0 to 1, and return from 1 to 0. These transitions are very important:
• The transition from 0 to 1 is defined as the positive edge (rising edge)
• The transition from 1 to 0 is defined as the negative edge (falling edge)
Based on which edge triggers the flip-flop, we have two types:
- Positive-edge triggered flip-flop: Changes state at the 0→1 transition
- Negative-edge triggered flip-flop: Changes state at the 1→0 transition
📝 Practice Questions — Triggering
Q1 (MCQ): The transition from 0 to 1 in a clock pulse is called:
A) Negative edge B) Positive edge C) Toggle D) Reset
Explanation: By definition, the positive transition (0 to 1) is called the positive edge, and the negative transition (1 to 0) is called the negative edge.
Q2 (MCQ): A momentary change in input signal that causes a flip-flop to change state is called:
A) Clock cycle B) Trigger C) Toggle D) Pulse width
Explanation: According to the PDF, “The state of the flip-flop is changed by a momentary change in the input signal. This momentary change is known as Trigger.” A toggle is a type of state change, but trigger is the correct term for the momentary input change.
Q3 (Write/Explain): Define positive edge and negative edge of a clock pulse.
A clock pulse goes through two signal transitions:
• Positive edge (rising edge): The transition from logic 0 to logic 1 (0 → 1). This is the point where the signal rises from low to high.
• Negative edge (falling edge): The transition from logic 1 to logic 0 (1 → 0). This is the point where the signal falls from high to low.
These edges are important because flip-flops can be designed to respond to either the positive edge or the negative edge of the clock pulse.
8. Comprehensive Exam Review Questions
Great job making it this far, students! Now let me test your understanding with some harder mixed questions. These are the type of questions that appear in actual Ethiopian university exams. Try to answer them before clicking “Show Answer”!
🔴 Hard Exam Questions — Mixed Topics
Q1 (MCQ): A combinational circuit differs from a sequential circuit in that a combinational circuit:
A) Uses flip-flops B) Has memory C) Has no memory of previous inputs D) Requires a clock signal
Explanation: A combinational circuit’s output depends only on the present combination of inputs, with no regard to previous inputs. Sequential circuits (which use flip-flops) have memory. Options A, B, and D all describe properties of sequential circuits, not combinational circuits.
Q2 (MCQ): If the output of a logic gate is the complement of the OR operation, the gate is:
A) NAND B) NOR C) XOR D) XNOR
Explanation: NOR = NOT-OR. It performs the OR operation first, then inverts (complements) the result. Expression: \(x = (A + B)’\). NAND is the complement of AND, not OR.
Q3 (MCQ): Which of the following Boolean expressions represents the carry output of a Full Adder?
A) \(x \oplus y \oplus z\) B) \(x \cdot y\) C) \(xy + z(x \oplus y)\) D) \(x + y + z\)
Explanation: Both \(xy + xz + yz\) and \(xy + z(x \oplus y)\) are equivalent forms of the Full Adder carry. Let’s verify: \(z(x \oplus y) = z(xy’ + x’y) = xy’z + x’yz\). Adding \(xy\): \(xy + xy’z + x’yz = xy(1 + z) + x’yz = xy + x’yz\). Also \(xy + xz + yz = xy + xz(1) + yz(1) = xy + xz + yz\). These simplify to the same expression. Option A is the Sum, B is Half Adder carry, and D is just a simple OR.
Q4 (MCQ): In a D flip-flop, if D = 1 and the clock pulse is HIGH, what will be the output Q?
A) 0 B) 1 C) Previous state D) Toggle
Explanation: In a D flip-flop, when the clock is HIGH, the output Q follows the D input. Since D = 1, Q = 1 (SET state). If D were 0, Q would be 0 (CLEAR state).
Q5 (Fill in the Blank): The number of rows in a truth table with 3 variables is ______.
Explanation: Number of rows = 2n = 23 = 8. This formula applies to any truth table with n variables.
Q6 (Fill in the Blank): The XOR gate gives output 1 when the two inputs are ______.
Explanation: XOR (Exclusive-OR) gives output 1 when exactly one input is 1 (inputs are different). It gives 0 when both inputs are the same (both 0 or both 1).
Q7 (Workout): A Full Adder has inputs x = 1, y = 1, z = 0. Calculate the Sum (S) and Carry (C) outputs.
Given: x = 1, y = 1, z = 0
Sum: \(S = x \oplus y \oplus z = 1 \oplus 1 \oplus 0\)
Step 1: \(1 \oplus 1 = 0\)
Step 2: \(0 \oplus 0 = 0\)
S = 0
Carry: \(C = xy + xz + yz = (1)(1) + (1)(0) + (1)(0) = 1 + 0 + 0 = 1\)
C = 1
Verification: 1 + 1 + 0 = 10 in binary → Sum = 0, Carry = 1. ✓
Q8 (List and Compare): Compare Computer Architecture and Computer Organization with at least four points of difference.
| Aspect | Computer Architecture | Computer Organization |
|---|---|---|
| Definition | Structure and behavior of functional modules | How hardware components are connected together |
| Design Level | High-level design | Low-level design |
| Concern | What the system does | How the system does it |
| Components | Instruction sets, Addressing modes, Data types, Cache optimization | Circuit design, Adders, Signals, Peripherals |
| View | Programmer’s view | Hardware engineer’s view |
| Design Order | Designed first | Designed based on architecture |
| Changeability | Same across a computer family | Can vary between different implementations |
Q9 (Workout): For the Boolean function \(F = A + B’C\), construct the truth table and identify in which rows the output F = 1.
| A | B | C | B’ | B’C | F = A + B’C |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 1 | 0 | 0 |
| 0 | 0 | 1 | 1 | 1 | 1 |
| 0 | 1 | 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 | 0 | 0 |
| 1 | 0 | 0 | 1 | 0 | 1 |
| 1 | 0 | 1 | 1 | 1 | 1 |
| 1 | 1 | 0 | 0 | 0 | 1 |
| 1 | 1 | 1 | 0 | 0 | 1 |
Q10 (MCQ): Two Half Adders can be combined to form a Full Adder. In such a construction, the second Half Adder takes as inputs:
A) The two original bits B) The Sum from first Half Adder and the carry input C) The two carry outputs D) The original bits and the carry input
Explanation: When building a Full Adder from two Half Adders:
• First Half Adder: Takes x and y as inputs → produces partial Sum (S₁ = x⊕y) and partial Carry (C₁ = x·y)
• Second Half Adder: Takes S₁ and z (carry input) as inputs → produces final Sum (S = S₁⊕z) and second Carry (C₂ = S₁·z)
• Final Carry: C = C₁ OR C₂ = C₁ + C₂
This is a classic exam question!
9. Final Summary — What to Remember for Your Exam
Congratulations, dear students! You have completed the entire introduction chapter. Let me now give you a quick summary of everything you must carry to the exam hall:
1. Architecture vs Organization:
• Architecture = WHAT (high-level, instruction sets, addressing modes, data types, cache)
• Organization = HOW (low-level, circuit design, adders, signals, peripherals)
• Architecture is designed FIRST
2. Seven Logic Gates:
• AND (dot), OR (plus), NOT (prime/complement), NAND, NOR, XOR (⊕), XNOR
• Know all truth tables by heart!
3. Boolean Algebra:
• Truth table rows = 2n
• Practice converting between expressions, truth tables, and logic diagrams
4. Combinational Circuits:
• No memory — output depends only on present inputs
• 6 design steps (problem → variables → symbols → truth table → simplify → diagram)
5. Half Adder: S = x⊕y, C = x·y (2 inputs, 2 outputs)
6. Full Adder: S = x⊕y⊕z, C = xy + xz + yz (3 inputs, 2 outputs)
7. Flip-Flops:
• S-R: Invalid when S=1, R=1
• D: No invalid state, Q follows D
• J-K: No invalid state, toggles when J=K=1
• T: Single-input J-K, toggles when T=1
8. Triggering:
• Positive edge = 0→1 transition
• Negative edge = 1→0 transition
I hope this lesson helped you understand the introduction of Computer Organization and Architecture clearly. Practice all the questions again and again — that is the secret to scoring high in your exam. Good luck, my dear students! You can do it! 💪